Testbench Generator:

This script generates a testbench template for VHDL'87 entities that you can cut and paste into a text file. It declares and instantiates your entity as a component and declares and connects signals. It also provides some formatting to align things. Please compile the file with your entity first as the parser in this script is not that sophisticated when errors are detected.

Source File:

for libraries:
use libraries from file
use std_logic_1164 only
 for signal declarations:
one signal or constant per line
list signals or constants per file
for component declaration:
one port or generic per line
list ports or generics per file
continuous list of ports or generics
 for generics:
include in declaration only
include in testbench entity
include as constants
for component instantiation:
one port or generic per line
continuous list of ports or generics
 for association list:
explicit
positional
wrap lists at characters per line